1. Field of the Invention
This invention relates to methods for calculating the parasitic capacitances between conductors of an integrated circuit.
2. Description of the Related Art
Parasitic capacitances associated with the conductive elements of densely packed circuits, such as very large scale integrated circuits (VLSIs), can result in unacceptable circuit performance. For example, they can significantly slow down the circuit operation, and particularly for analog circuits can produce cross-talk between conductors. It is very desirable to calculate parasitic capacitances from the circuit layout to determine whether they exceed the design criteria. If calculated capacitances are excessive, the design can be corrected before committing to the time consuming and costly circuit fabrication process.
A calculation technique has been established to determine capacitances between conductors located in three dimensions. The technique is described in Ruehli and Brennan, "Efficient Capacitance Calculations for 3-Dimensional Multi-Conductor Systems", IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-21, No. 2, February 1973, pages 76-82 and in van der Meijs and van Genderen, "An Efficient Finite Element Method for Submicron IC Capacitance Extraction", 26th ACM/IEEE Design Automation Conference, Paper 40.2, 1989, pages 678-681. It involves a determination of a potential coefficient (the quantity that yields the voltage across capacitor plates when multiplied by the charge on the plates) matrix between the various conductors in the analysis. The potential coefficient matrix is inverted to obtain a short circuit capacitance matrix, from which an equivalent circuit capacitance matrix is derived that is normally used in a circuit simulation.
Two types of software approaches to parasitic capacitance calculation and extraction have been developed. The first type allows for the automatic calculation of parasitic capacitances based upon a geometrical description of a chip contained in a layout data base. This approach considers only interactions between two conductors at a time, ignoring the important effects of other nearby conductors. While a large circuit with many conductors can be analyzed, the failure to model the actual fringing electrical fields between conductors, or to account for multi-electrode interactions among all of the conductors, seriously degrades the accuracy of the results. Some parasitic capacitances are not detected at all, while others are overestimated by well over 100%. This approach is used in the PDextract system provided by CADENCE Design Systems of San Jose, Calif., as described in its Physical Design Verification Reference Manual, Version 2-1, Jun. 5, 1989, pages 5-32 through 5-48.
The other type of software, designated as the CASSE Parasitic Parameters program, is described in Pacific Numerix Corporation, Parasitic Parameters User's Manual, as revised Aug. 10, 1989. It uses the Ruehli and Brennan approach to consider the interactions among all parts of the entire circuit, and extends it to non-Manhattan-oriented geometries with a numerical integration technique for oblique lines. This gives accurate results, but the maximum circuit size that can be analyzed is severely limited because the computer memory requirements increase roughly in proportion to the square of the chip area. This type of software is not designed for automated extraction from a CAD (computer aided design) layout data base, but rather requires extensive manual input. Since the efficiency of the program is maximized when as many of the conductors as possible are "Manhattan-oriented" rectangles (rectangles arranged in a grid matrix), conductors with non-Manhattan rectangle geometries are handled by calculating a division of such conductors into many small rectangular pieces. This "fracturing" technique often produces a very large number of small rectangles, which further limits the ability of the program to handle larger circuits. A system that is similar to the CASSE Parasitic Parameters program, and also requires a great amount of computational time for larger circuits, is disclosed in Janak and Ling, "C3DSTAR: A 3D Wiring Capacitance Calculator", IEEE ICCAD-89 Digest, November 1989, pages 530-533.